For reasons of portability and convenience, more and more systems are being designed for use with battery power rather than line power. Unfortunately, such systems cause inconvenience to the user because the batteries must either be replaced or recharged periodically. Even for an electronic system powered by line, it is also desirable to reduce the power consumption thereby reduce the heat dissipated for reliability reasons. As a result, it is a common goal to design circuits that consume less power. Examples of systems where low power consumption is being actively sought include portable computers such as laptop or palmtop computers, personal digital assistants (PDAs), and wireless communications devices such as cellular telephones and pagers.
In the field of integrated circuits, a commonly used technique for reducing power consumption is to manufacture the circuit using CMOS circuit technology. CMOS circuits have the advantage that there is no path for current to flow in a steady state condition. However, it is well known that even CMOS circuits provide a current path during a transition from one logical state to another.
Within each electronic system or integrated circuit, there are many sub-circuits or functional blocks which all work together to perform desired operations. Each sub-circuit in the system is synchronized by a clock. For certain types of circuits, including CMOS circuits, power consumption is increased when the circuits are exercised by a clock signal. As a result of the clock signal, even CMOS circuits draw power.
In order to reduce the power consumption of electronic systems, the frequency of the system clock can be reduced when high speed operation is not required in some applications. This can be achieved by using a PLL whose output frequency can be changed easily compared to a fixed frequency generated by a crystal oscillator. When high speed operation is required for certain applications, the clock frequency generated by a PLL can be increased.
Typical electronic systems employ multiple integrated circuit chips or functional blocks. Each chip or block typically performs a limited number of functions for the system, for example, to control a semiconductor memory, to control a hard disk, to control a screen display and other related functions. Periodically, some of these circuits are not needed and are inactive insofar as system functionality is concerned. To save power further, the clock signal to such circuits can be disabled during the idle period. While this does reduce power consumption, the circuit that generates the clock signal still operates and thus draws power.
One method used to reduce the time that the clock signal is supplied to an integrated circuit is used in PCMCIA Host Adapters, part Nos. C1-PD6710/PD672X, which are supplied by Cirrus Logic, Inc. of Fremont, Calif. This method teaches simultaneously disabling the clock signal to all of the functional blocks, after all of the functional blocks have signalled that they no longer require the clock signal. An arbiter circuit then monitors the system bus and will re-enable the clock signal to all of the functional blocks simultaneously, when an address within the range controlled by the arbiter and a corresponding command are present on the system bus. The disadvantage of this system is that the power savings can only be realized when the entire circuits of the C1-PD6710/PD672X become temporarily inactive.
The reason not to power down the PLL when the output of the PLL is disabled is that a conventional PLL cannot output the desired frequency immediately after the power down period. With conventional PLL, when the PLL is enabled after a power-down reset period, it can take up to 30 phase comparisons to regain the designed frequency. A phase comparison usually takes about 1 .mu.S depending on the reference frequency so that the PLL can only recover in approximately 30 .mu.S. This recovery time may be too slow for certain applications. In addition, the lengthy recovery time also prevents the PLL from powering down as often as possible to reduce the power consumption.
Another unrelated problem also presently exists for designers of integrated circuits. It is generally not possible to build an integrated circuit that includes two PLLs. Cross talk between the two PLLs prevents the two circuits from maintaining their respective designed frequencies. As discussed above, there is a significant delay in restarting a PLL from rest. Thus, it has not been practical to design an integrated circuit with two PLLs and alternatively deactivate one PLL; it takes too long for the clock signal to regain the desired frequency.
What is needed is a PLL circuit that can be temporarily disabled in order to reduce the power consumption. However, the PLL can be activated again and resume operation immediately at its designed frequency. It is further desirable that during a power-down idle mode, the PLL can be activated for a single phase comparison (refresh itself) and then de-activate again automatically.